Priyank Faldu

PhD Student, University of Edinburgh

I am a fourth year PhD student at the University of Edinburgh in School of Informatics working under supervision of Dr. Boris Grot . My research interestes lie in the field of Computer Architecture and I am affiliated with two groups - ICSA & CArD.

I am interested in challenging problems in the space of cache/memory hierarchy. At present, I am working on designing efficient cache management techniques for applications with varied characteristics that cover general purpose single-core and multi-core applications, multi-threaded scale-out server applications and modern graph analytics applications.

My research interests span various aspects of system designs. In my career, I have worked on various projects that include microarchitecture enhancements, simulator design & implementation, workload characterization for bottleneck analysis, debugging performance issues on real hardware, programming parallel softwares, accelerating applications using GPU via OpenCL/CUDA etc.


  • Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches [PACT'17] [Acceptance Rate: 23%]
    Priyank Faldu and Boris Grot
    In Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, September 2017.
  • Reuse-Aware Management for Last-Level Caches [CRC'17]
    Priyank Faldu and Boris Grot
    In 2nd International Workshop on Cache Replacement Championship, co-located with ISCA, June 2017.
  • LLC Dead Block Prediction Considered Not Useful [WDDD'16]
    Priyank Faldu and Boris Grot
    In 13th International Workshop on Duplicating, Deconstructing and Debunking, co-located with ISCA, June 2016.


  • Cache Memory Architecture and Policies for Accelerating Graph Algorithms
    Priyank Faldu , Jeffrey Diamond and Avadh Patel
    U.S. Patent: 20180129613, Assignee: Oracle International Corporation, Issued: May 10, 2018
  • Parallelization Method and Electronic Device
    Jaehan Koh, Anuradha Oberoi, Gopalakrishna Puligedda Sharma, Raghavan Velappan and Priyank Faldu
    U.S. Patent: 20160004570, Assignee: Samsung Electronics Co., Ltd., Issued: January 7, 2016


  • Challenges in Scaling Up Graph Analytics
    Priyank Faldu and Boris Grot
    At 3rd Annual UK System Research Challenges Workshop, March 2018.


  • Oracle ERO Award: Efficient Scale-Up Graph Processing on Future Memory Systems
    Co-authored the grant proposal; PI: Boris Grot; Award: $76,000; Year: 2017


Professional Experience

  • Samsung R & D Institute, Bangalore - India
    Lead Engineer July 2013 - August 2014
  • Intel Corporation, Bangalore - India
    Graphics Hardware Engineer May 2011 - July 2013
  • Google Inc, Bangalore - India
    Software Engineer July 2010 - March 2011


  • Oracle Labs, Austin - U.S.A.
    Research Assistant May 2016 - September 2016
  • Tata Consultancy Services, Gandhinagar - India
    Software Engineer January 2008 - April 2008

Awards & Recognitions

  • Received School of Informatics PhD Scholarship
  • Received Academic Excellence Award at IIT Kanpur for the year 2008-09
  • Topper of the M.Tech. batch 2008-10, IIT Kanpur
  • All India Rank 440 and 263 in Graduate Aptitude Test in Engineering (GATE) 2007 and 2008 respectively

Academic & Professional Activities